Low Cost Journal,International Peer Reviewed and Refereed Journals,Fast Paper Publication approved journal IJEDR(ISSN 2321-9939)
apply for ugc care approved journal, UGC Approved Journal, ugc approved journal, ugc approved list of journal, ugc care journal, care journal, UGC-CARE list, New UGC-CARE Reference List, UGC CARE Journals, ugc care list of journal, ugc care list 2020, ugc care approved journal, ugc care list 2020, new ugc approved journal in 2020,
Low cost research journal, Online international research journal, Peer-reviewed, and Refereed Journals, scholarly journals, impact factor 7.37 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool)
Design and Implementation of Parallel AES Encryption Engines for Multi-Core Processor Arrays
M.Samba Siva Reddy,  P.James Vijay,  B. Murali Krishna
Abstract: By exploring different granularities of data-level and task-level parallelism, we map 4 implementations of an Advanced Encryption Standard (AES) cipher with both online and offline key expansion on a fine-grained many-core system. The smallest design utilizes only six cores for offline key expansion and eight cores for online key expansion, while the largest requires 107 and 137 cores, respectively. In comparison with published AES cipher implementations on general purpose processors, our design has 3.5-15.6 times higher throughput per unit of chip area and 8.2-18.1 times higher energy efficiency. Most AES calculations are done in a special field. The AES cipher is specified as a number of repetitions of transformation rounds that convert the input plain-text into the final output of cipher-text. Each round consists of several processing steps, including one that depends on the encryption key. A set of reverse rounds are applied to transform cipher-text back into the original plain-text using the same encryption key.
Keywords- Key words-- Advanced Encryption Standard, Sub bytes, Shift row, mixed column, Add round Key and Parallel AES.
Unique Identification Number - IJEDR1404042Page Number(s) - 3656-3661Pubished in - Volume 2 | Issue 4 | Dec 2014DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
M.Samba Siva Reddy,  P.James Vijay,  B. Murali Krishna,   "Design and Implementation of Parallel AES Encryption Engines for Multi-Core Processor Arrays"
, International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 4, pp.3656-3661, Dec 2014, Available at :http://www.ijedr.org/papers/IJEDR1404042.pdf