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Paper Details
Paper Title
Design and Implementation of Parallel AES Encryption Engines for Multi-Core Processor Arrays
Authors
  M.Samba Siva Reddy,  P.James Vijay,  B. Murali Krishna
Abstract
Abstract: By exploring different granularities of data-level and task-level parallelism, we map 4 implementations of an Advanced Encryption Standard (AES) cipher with both online and offline key expansion on a fine-grained many-core system. The smallest design utilizes only six cores for offline key expansion and eight cores for online key expansion, while the largest requires 107 and 137 cores, respectively. In comparison with published AES cipher implementations on general purpose processors, our design has 3.5-15.6 times higher throughput per unit of chip area and 8.2-18.1 times higher energy efficiency. Most AES calculations are done in a special field. The AES cipher is specified as a number of repetitions of transformation rounds that convert the input plain-text into the final output of cipher-text. Each round consists of several processing steps, including one that depends on the encryption key. A set of reverse rounds are applied to transform cipher-text back into the original plain-text using the same encryption key.
Keywords- Key words-- Advanced Encryption Standard, Sub bytes, Shift row, mixed column, Add round Key and Parallel AES.
Publication Details
Unique Identification Number - IJEDR1404042Page Number(s) - 3656-3661Pubished in - Volume 2 | Issue 4 | Dec 2014DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  M.Samba Siva Reddy,  P.James Vijay,  B. Murali Krishna,   "Design and Implementation of Parallel AES Encryption Engines for Multi-Core Processor Arrays", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 4, pp.3656-3661, Dec 2014, Available at :http://www.ijedr.org/papers/IJEDR1404042.pdf
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