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INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH
(International Peer Reviewed,Refereed, Indexed, Citation Open Access Journal)
ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
A new 4 Bit Asynchronous Counter using Novel Low power explicit type pulse-triggered Delay Flip Flop (D-FF)
Authors
  Shashank Uniyal,  Vishal Ramola

Abstract
The Flip flop circuit is one of the most significant part in VLSI Low power circuits which is used as a basic storage element. In this paper we implemented a new 4 bit asynchronous counter using modified Low power explicit type pulse triggered delay flip-flop (D-FF) design. The modified design effectively tackles the long discharging path issue in conventional flip flop designs to accomplish better speed, power performance and avoid superfluous Q_fdbk transistor. The execution has been explored utilizing 90nm Technology at 1.8V and assessed by comparison of the simulation result obtain from TSPICE.

Keywords- Flip-Flop Ep-DCO, CDFF, Static SDFF, MHLFF, Propagation Delay, Power Consumption and Power Delay Product (PDP)
Publication Details
Unique Identification Number - IJEDR1503012
Page Number(s) -
Pubished in - Volume 3 | Issue 3 | July 2015
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Shashank Uniyal,  Vishal Ramola,   "A new 4 Bit Asynchronous Counter using Novel Low power explicit type pulse-triggered Delay Flip Flop (D-FF)", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 3, pp., July 2015, Available at :http://www.ijedr.org/papers/IJEDR1503012.pdf
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