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Paper Title
Integrating MRPSOC with Multigrain Parallelism for Improvement of Performance
  Swathi S T,  Kavitha V

There are several techniques to reconfigure the instruction set processors. One such technique is Multi Reconfigurable Instruction Set Processor System on Chip (MRPSOC). Integrating MRPSOC with multigrain parallelism for improvement of performance is done in this paper. By using MRPSOC, performance of the system is increased. Multimedia application computing can be accelerated by using multigrain parallelism. By implementing this integrated processor extra feature can be added to MRPSOC. Multiple data is packed in a single register which forms a vector; this vector of multiple data is fetched to MRPSOC at a time. Since MRPSOC is a combination of MPSOC and RISP processor, instruction level parallelism can be implemented in MRPSOC. After execution of operations in MRPSOC the multiple outputs can be stored at different memory locations of a same memory system simultaneously. This thesis is aimed to design MRPSOC interfaced with data level, instruction level and memory transfer level parallelism. Form this paper it is concluded that by using both MRPSOC and multigrain parallelism in common platform high speed computation can be achieved

Keywords- Reconfigurable Instruction set Processors (RISP), Multigrain parallelism , Multi Reconfigurable Instruction set processor system on chip(MRPSOC)
Publication Details
Unique Identification Number - IJEDR1503066
Page Number(s) -
Pubished in - Volume 3 | Issue 3 | August 2015
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
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  Swathi S T,  Kavitha V,   "Integrating MRPSOC with Multigrain Parallelism for Improvement of Performance", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 3, pp., August 2015, Available at :http://www.ijedr.org/papers/IJEDR1503066.pdf
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