Low Cost Journal,International Peer Reviewed and Refereed Journals,Fast Paper Publication approved journal IJEDR(ISSN 2321-9939) apply for ugc care approved journal, UGC Approved Journal, ugc approved journal, ugc approved list of journal, ugc care journal, care journal, UGC-CARE list, New UGC-CARE Reference List, UGC CARE Journals, ugc care list of journal, ugc care list 2020, ugc care approved journal, ugc care list 2020, new ugc approved journal in 2020, Low cost research journal, Online international research journal, Peer-reviewed, and Refereed Journals, scholarly journals, impact factor 7.37 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool)
(International Peer Reviewed,Refereed, Indexed, Citation Open Access Journal)
ISSN: 2321-9939 | ESTD Year: 2013

Current Issue

Call For Papers
June 2023

Volume 11 | Issue 2
Last Date : 29 June 2023
Review Results: Within 12-20 Days

For Authors


Indexing Partner

Research Area


Paper Details
Paper Title
Reduction of Leakage Power of Full Adder using Variable Body Biasing with sleep insertion Technique
  Sunita Yadav,  Vishal Ramola

Reduction of leakage Power is the major problem in digital circuits. There are various techniques that are used to reduce the leakage power. Variable Body Biasing technique is discussed in this paper. Variable body biasing technique with sleep insertion technique is one of the efficient technique for designing combinational digital circuits which significantly cuts down the leakage current without increasing the dynamic power dissipation, sleep insertion technique is also added along with variable body biasing technique so that there is no loss of state as in sleep stack technique. This thesis proposed a technique that reduces both power dissipation and glitches. This technique is based on two methods first is variable body biasing and the other is sleep insertion technique. Pass transistor is also added in the circuitry in order to eliminate glitches if any. The existing leakage reduction techniques like sleepy keeper and stack technique are having drawbacks like increased area and delay. Other delay elements that are used for reduction in glitches takes larger area when compared with pass transistor. This new proposed approach eliminates leakage power along with glitches keeping in mind all the drawbacks of all the earlier techniques. All the performance has been investigated using 90nm Technology at 1 voltage and evaluated by the comparison of the simulation result obtain from TSPICE.

Keywords- VBBT, Delay, leakage power, sleep insertion technique
Publication Details
Unique Identification Number - IJEDR1503070
Page Number(s) -
Pubished in - Volume 3 | Issue 3 | August 2015
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Sunita Yadav,  Vishal Ramola,   "Reduction of Leakage Power of Full Adder using Variable Body Biasing with sleep insertion Technique", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 3, pp., August 2015, Available at :http://www.ijedr.org/papers/IJEDR1503070.pdf
Share This Article

Article Preview

ISSN Details

DOI Details

Providing A digital object identifier by DOI
How to get DOI?

For Reviewer /Referral (RMS)

Important Links

NEWS & Conference

Digital Library

Our Social Link

© Copyright 2023 IJEDR.ORG All rights reserved