Optimization of Design Parameters in Nanoscale Reconfigurable FET for Improved Performance

  K.Sandhyarani,  Ch.Sathyanarayana

As we are approaching the limits of scaling, Scaling down the thickness of gate oxide is not found to be a good idea, as it causes a reduction in ON–OFF current ratio though S/S remains mostly unaffected. so we propose the impact of variation in design parameters, such as spacer length and spacer material type, gate dielectric and its thickness, and integrate distance on the device performance of a DG spacer-based silicon nanowire ambipolar FET (SiNWFET),has been carried out for the first time. The design of spacer-based potentially improved reconfigurable FET devices for future low-power CMOS applications. It reports various optimization aspects of an ambipolar silicon nanowire field-effect transistor with high-κ source–drain (S/D) spacer using coupled 3-D Technology.

Keywords- SiNWFET, Spacer, ambipolarity, variability, high- k.

Unique Identification Number - IJEDR1604022
Page Number(s) - 120-125
Pubished in - Volume 4 | Issue 4 | October 2016
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  K.Sandhyarani,  Ch.Sathyanarayana,   "Optimization of Design Parameters in Nanoscale Reconfigurable FET for Improved Performance", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.4, Issue 4, pp.120-125, October 2016, Available at :http://www.ijedr.org/papers/IJEDR1604022.pdf