Design of Hierarchy Multiplier Based on Vedic mathematics using CSLA and BEC

  B.Farshana,  P.Nagarajan,  S.Manikandan

Hierarchy multiplier has the ability to carry the multiplication operation within one clock cycle. The existing hierarchical multipliers occupy more area and also results in more delay. A method to lower the computation delay of hierarchy multiplier by using Carry select adder (CSLA) and Binary to Excess 1 Converter (BEC) is proposed. The BEC removes the n/4 number of adders, existing in the conventional addition scheme, where n indicates the multiplier input width. Then the area of the hierarchy multiplier is determined by its base multiplier, the base multiplier is realized with the proposed Vedic multiplier, this has small area and operates with less delay than the conventional multipliers. Furthermore the reduction of power consumption in the hierarchy multiplier can be confirmed by implementing the designed multiplier with full swing Gate Diffusion Input (GDI) logic. The Cadence SPICE simulator using 45 nm technology model has used to analyses the performances of the proposed and also the existing multipliers.

Keywords- vedic multiplier, Binary to Excess 1 converter,Carry Select Adder

Unique Identification Number - IJEDR1604074
Page Number(s) - 502-506
Pubished in - Volume 4 | Issue 4 | November 2016
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  B.Farshana,  P.Nagarajan,  S.Manikandan,   "Design of Hierarchy Multiplier Based on Vedic mathematics using CSLA and BEC", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.4, Issue 4, pp.502-506, November 2016, Available at :http://www.ijedr.org/papers/IJEDR1604074.pdf