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Paper Title
Design Of SoC Using 64 Bit RISC Processor For Packaging Industry
  Rupali V. Bhange,  Prof. Yogesh M. Motey

In the era of industrialization, technological revolution reduced the intervention of humans to assist machinery. The privatization slogan has increased the competition among industries which leads to origin of new products/designs for automation. The paper presents, one such, design and implementation of 64-bit RISC processor on SOC for industry automation, mainly useful for packing. The design includes processor with BIST features; it is a mechanism that allows a machine to test itself. Here RISC processor is used to decrease the number of instructions and they execute the instruction at faster rate. Later the design is integrated on System on Chip (SoC) to obtain a single chip which reduces the overall power consumption. The design and synthesis is done by verilog and verified in Altera Quartus 11.0 RTL compiler, SoPC Builder, Nios II SBT Eclipse, and Modelsim 10.1c.

Keywords- industrial automation, reduced instruction set computer, system-on-chip, handling and packaging, synthesis, simulation, verification, hardware description language
Publication Details
Unique Identification Number - IJEDR1702139
Page Number(s) - 839-844
Pubished in - Volume 5 | Issue 2 | May 2017
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Rupali V. Bhange,  Prof. Yogesh M. Motey,   "Design Of SoC Using 64 Bit RISC Processor For Packaging Industry", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 2, pp.839-844, May 2017, Available at :http://www.ijedr.org/papers/IJEDR1702139.pdf
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