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Paper Details
Paper Title
Implementation of Scan Insertion and Compression for 28nm design Technology
Authors
Mohan PVS, Rajanna K.M
Abstract
Scan Insertion and Scan Compression are necessary for design-for-testability (DFT) methodology, which helps to achieve very high quality testability feature for the design at low costs. Scan Insertion methodology is improving over the years and the Scan Compression is improving and meeting the needs by providing the testability feature for the designs. In this paper, the implementation of the Scan Insertion and Compression techniques in the 28nm technology is been presented. We implemented Scan Insertion and compression technology and also, we discuss about the clock and reset DRCs and how the compression help in testing the integrated circuit by reducing the test time and test data volume.
Keywords-
Publication Details
Unique Identification Number - IJEDR1703147Page Number(s) - 1043-1050Pubished in - Volume 5 | Issue 3 | September 2017DOI (Digital Object Identifier) - Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Mohan PVS, Rajanna K.M, "Implementation of Scan Insertion and Compression for 28nm design Technology", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 3, pp.1043-1050, September 2017, Available at :http://www.ijedr.org/papers/IJEDR1703147.pdf
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