Design of Modified Booth Encoder based Low Power Multiplier

  Suresh H,  Beena A O

Multipliers are one of the major power consuming elements in digital signal processing applications. Multiplications occur in digital signal processing applications like FIR filters, FFT, DCT, convolution etc. The use of a low power multiplier will provide a significant reduction in power for the digital signal processing applications. This paper discuss about the design of a low power multiplier based on Booth encoding technique and Spurious Power Suppression Technique (SPST). A normal multiplier performs the multiplication operation by repeated shifting and addition process. For an n-bit multiplier there will be n additions of n-bit numbers. In this design the Booth encoding technique reduces the number of additions by half and the SPST reduces the unwanted transitions in the adder.

Keywords- booth encoder, spurious power supperssion technique, low power.

Unique Identification Number - IJEDR1801135
Page Number(s) - 784-788
Pubished in - Volume 6 | Issue 1 | March 2018
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Suresh H,  Beena A O,   "Design of Modified Booth Encoder based Low Power Multiplier", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.6, Issue 1, pp.784-788, March 2018, Available at :http://www.ijedr.org/papers/IJEDR1801135.pdf