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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
FPGA Implementation Of Modified AES Algorithm For Improved Timing
Authors
  Qazi Sama,  Er.Sandeep Sangwan

Abstract
This Paper presents Pipelined and LUT based crypto multiplication implementation of high speed AES algorithm using Verilog. The proposed architecture is based on optimizing timing in terms of adding inner and outer pipeline registers for each rounds and Key Expansions. Further by optimizing the Crypto Multiplication for Mix columns via LUT based approach aid in further optimization in terms of timing, LUT and Pipelined based implementation techniques are optimal for FPGA based implementations. ROM table and pipelining are the two techniques used to implement AES. With the use of fully pipelined architecture and Distributed/Split LUT-Pipelined techniques, the throughput and speed of the encryption is increased tremendously. Xilinx ISE 14.7 ISE is used for synthesis and simulation of this proposed architecture. Xilinx Vivado can also be used to obtain results for ultra-scale devices, Implementation results are obtained for a Spartan6 Family of FPGA.

Keywords- AES, Sub bytes, Mix columns, LUT, Verilog HDL, FPGA, Speed, Pipelined, crypto multiplication
Publication Details
Unique Identification Number - IJEDR1803090
Page Number(s) - 528-534
Pubished in - Volume 6 | Issue 3 | September 2018
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Qazi Sama,  Er.Sandeep Sangwan,   "FPGA Implementation Of Modified AES Algorithm For Improved Timing", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.6, Issue 3, pp.528-534, September 2018, Available at :http://www.ijedr.org/papers/IJEDR1803090.pdf
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