Low Cost Journal,International Peer Reviewed and Refereed Journals,Fast Paper Publication approved journal IJEDR(ISSN 2321-9939)
apply for ugc care approved journal, UGC Approved Journal, ugc approved journal, ugc approved list of journal, ugc care journal, care journal, UGC-CARE list, New UGC-CARE Reference List, UGC CARE Journals, ugc care list of journal, ugc care list 2020, ugc care approved journal, ugc care list 2020, new ugc approved journal in 2020,
Low cost research journal, Online international research journal, Peer-reviewed, and Refereed Journals, scholarly journals, impact factor 7.37 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool)
Parallel Pipelined C-Slow Retimed Architecture through an Efficient Systolic Array
G.Shanmugaraj,  Narender Malishetty,  G.Sethuram Rao
A fully parallel pipelined array of cells is proposed for suitable real-time calculation of histograms. The cell structure builds on earlier work to now agree operating on a stream of data at single pixel per unit clock cycle. This novel cell is more fitting for interfacing to sensors of camera or to microprocessors of 8- or 16-bit data buses which are commonly used by consumer digital cameras. Image analysis created on histograms is copious and fully utilized in many consumer applications. The proposed architectures for systolic arrays and also make available a general method for mapping an algorithm to a systolic array. An array of cells to achieve the computation of n-bin histograms that takes p pixels per unit clock cycle offers to improvement a speedup factor of p. Likewise a design was proposed, but then required a sensor or processor providing four pixels per unit clock cycle to get a speedup in terms of four. Many real time embedded microprocessors contain of 8 bit data buses or 16 bit data and subsequently are able to supply one pixel per clock cycle. So as to feat this property, the proposed work is a histogram outcome using C-slow retiming to produce two sub streams of computation resulting from a dataset received at one pixel per unit clock cycle. Here proved that Arrays using the new proposed cells are obtained through C slow technique. Retiming techniques used at a faster frequency than earlier arrays.
Keywords- Embedded, Microprocessor, Parallel, Pipelined, Retiming.
Unique Identification Number - IJEDR1904084Page Number(s) - 471-475Pubished in - Volume 7 | Issue 4 | December 2019DOI (Digital Object Identifier) -    http://doi.one/10.1729/Journal.22978Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
G.Shanmugaraj,  Narender Malishetty,  G.Sethuram Rao,   "Parallel Pipelined C-Slow Retimed Architecture through an Efficient Systolic Array"
, International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.7, Issue 4, pp.471-475, December 2019, Available at :http://www.ijedr.org/papers/IJEDR1904084.pdf