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Paper Title
EFFECIENT MAJORITY LOGIC FAULT DETECTOR/CORRECTOR USING EUCLIDEAN GEOMETRYUSING LOW DENSITY PARITY CHECK CODES
Authors
  RAHILA BEGUM U,  V.PADMAJOTHI

Abstract
Error detection in memory applications was proposed to accelerate the majority logic decoding of difference set low density parity check codes. This is useful as majority logic decoding can be implemented serially with simple hardware but requires a large decoding time. For memory applications, this increases the memory access time. The method detects whether a word has errors in the first iterations of majority logic decoding, and when there are no errors the decoding ends without completing the rest of the iterations. Since most words in a memory will be error free, the average decoding time is greatly reduced. In this brief, the application of a similar technique to a class of Euclidean geometry low density parity check (EG-LDPC) codes that are one step majority logic decodable. The results obtained show that the method is also effective for EG-LDPC codes. Extensive simulation results are given to accurately estimate the probability of error detection for different code sizes and numbers of errors.

Keywords- -
Publication Details
Unique Identification Number - IJEDR1402038
Page Number(s) - 1522-1527
Pubished in - Volume 2 | Issue 2 | June 2014
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  RAHILA BEGUM U,  V.PADMAJOTHI,   "EFFECIENT MAJORITY LOGIC FAULT DETECTOR/CORRECTOR USING EUCLIDEAN GEOMETRYUSING LOW DENSITY PARITY CHECK CODES", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 2, pp.1522-1527, June 2014, Available at :http://www.ijedr.org/papers/IJEDR1402038.pdf
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