FPGA Implementation of a high speed Vedic Multiplier

  Vittal Kamath,  Tanya Wanchoo,  Sudheendra Prabhu

Since most of the important DSP algorithms such as Fast Fourier Transforms, Convolution etc incorporate complex multiplication computations, the overall time utilized is high. In the proposed design we have implemented a vedic multiplier using the ‘Urdhva Tiryagbhyam’ and ‘Nikhilam Navatashcaramam Dashatah’ sutras, resulting in the reduction of delay in the multiplier thereby increasing the overall speed of the system. HDL designer version 2012.1 has been used for coding which is synthesized using Xilinx device Spartan-3 MXS3FK-PQ208 FPGA. Results indicate 14% reduction in time delay when compared to a conventional multiplier.

Keywords- Vedic Mathematics, Urdhva Tiryagbhyam Sutra, Carry-skip technique

Unique Identification Number - IJEDR1402082
Page Number(s) - 1796-1803
Pubished in - Volume 2 | Issue 2 | June 2014
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Vittal Kamath,  Tanya Wanchoo,  Sudheendra Prabhu,   "FPGA Implementation of a high speed Vedic Multiplier", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 2, pp.1796-1803, June 2014, Available at :http://www.ijedr.org/papers/IJEDR1402082.pdf