Studying Impact of Transistor Aging and Process Parameter Variation on the Performance of Analog Circuits
Hemant Madan Khadilkar
NBTI and HCI emerged as a major reliability concern for deep-submicron CMOS technology. For 65nm technology, process parameter variation is also creating problems for reliable design. We report simulation study for NBTI mechanism for PMOS and HCI for NMOS. Comparator circuit is used to study the impact of NBTI on offset voltage. The process parameter variation is also studied. Offset voltage is modeled in terms of process parameters and effect and sensitivity for these process parameters has been studied.
Keywords- NBTI, reliability, process parameter variation, Design of Experiment (DOE)
Cite this Article
Hemant Madan Khadilkar,   "Studying Impact of Transistor Aging and Process Parameter Variation on the Performance of Analog Circuits"
, International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 2, pp.2908-2912, June 2014, Available at :http://www.ijedr.org/papers/IJEDR1402258.pdf