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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Reversible Circuit Using Reversible Gate
  Pooja Rawat,  Vishal Ramola

Abstract –Reversible logic is very promising due to its low power consumption. There are no. of works have been reported on reversible combinational circuit design. However less work on sequential circuit. This paper proposes the following:1) Construction of Basic Reversible Logic Gate and using these gate construct reversible sequential circuit. 2) Construction and Comparisons of R1 based decoder circuit with proposed decoder circuit in term of delay. The proposed structure has been designed and simulated on XILINX 12.2 tool in Verilog language. Index Terms –reversible logic and gates, flip flop, garbage, sequential circuit.

Publication Details
Unique Identification Number - IJEDR1602182
Page Number(s) - 1041-1046
Pubished in - Volume 4 | Issue 2 | May 2016
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Pooja Rawat,  Vishal Ramola,   "Reversible Circuit Using Reversible Gate", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.4, Issue 2, pp.1041-1046, May 2016, Available at :http://www.ijedr.org/papers/IJEDR1602182.pdf
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