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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Details
Paper Title
128 *128 SRAM in Cooperating Ultra Low Power Technique
Authors
  Mitali Agarwal ,  Taru Tavatiyia,  Nitin Sehgal

Abstract
he primary technique used for power reduction is self-timed architecture. Memory timing circuits need a delay element which tracks the bit-line delay but still provide a large swing signal which can be used by the subsequent stages of the control logic. The key to building such a delay stage is to use a delay element which is a replica of the memory cell connected to the bit-line, while still providing a full swing output. This technique uses a dummy column and dummy row in the RAM to control the flow of signals through the core. This section explores the self-timed technique for the SRAM. The circuit diagram of self-timed IO block .The technique for achieving this uses a “dummy column” in the RAM to control the flow of signals through the core. A dummy column is an additional column of bit-cells. Bit-cells in the dummy column are forced to a known state by shorting one of the internal nodes to a given voltage.

Keywords- Ultra low power SRAM, Row Decoder ,Sense amplifier ,Write driver circuit.
Publication Details
Unique Identification Number - IJEDR1602298
Page Number(s) - 1678-1681
Pubished in - Volume 4 | Issue 2 | June 2016
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Mitali Agarwal ,  Taru Tavatiyia,  Nitin Sehgal,   "128 *128 SRAM in Cooperating Ultra Low Power Technique", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.4, Issue 2, pp.1678-1681, June 2016, Available at :http://www.ijedr.org/papers/IJEDR1602298.pdf
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