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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Design Of Approximate Multiplier With Tradeoff In Power And Area
Authors
  I.Rinisha Prem Priya,  Dr.J. Ajayan

Abstract
Approximation circuit’s offer superior performance (delay and area) compared to traditional circuits at the cost of computational accuracy. Three stages can be identified in a multiplier: partial product generation, partial product reduction, and final addition. The state-of-the-art approximate multipliers that provide the best trade-off between quality and other design parameters such as power and delay. The proposed approximate multiplier achieves a improved area and delay. By improving delay and area the performance of BAM multiplier is improved. Approximate unsigned multipliers are comparatively evaluated for both error and circuit characteristics.

Keywords- Approximate computing circuits and systems,broken array multiplier,approximate multipliers.
Publication Details
Unique Identification Number - IJEDR1902027
Page Number(s) - 122-125
Pubished in - Volume 7 | Issue 2 | May 2019
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  I.Rinisha Prem Priya,  Dr.J. Ajayan,   "Design Of Approximate Multiplier With Tradeoff In Power And Area", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.7, Issue 2, pp.122-125, May 2019, Available at :http://www.ijedr.org/papers/IJEDR1902027.pdf
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