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Paper Details
Paper Title
Low power explicit type pulse-triggered FF (P-FF) design at Minimum Transistor
Authors
Shashank Uniyal, Rajeev Kumar, Krishna Chandra, Vishal Ramola
Abstract
The Flip flop circuit is one of the major component in VLSI Low power circuits. In this paper we modified (proposed) a Low power explicit type pulse triggered flip-flop (P-FF) design based on single feed through scheme. The modified design successfully solves the long discharging path problem in conventional flip flop designs to achieve better speed, power performance and avoids unnecessary Q_fdbk transistor. We also design 4-bit Shift Resistor using modified P-FF. The performance has been investigated using 90nm Technology at 1.8 voltage and evaluated by the comparison of the simulation result obtain from TSPICE.
Keywords- Flip Flop-Ep-DCO, CDFF, Static SDFF, MHLFF, Propagation Delay, Power Consumption Power Delay Product.
Publication Details
Unique Identification Number - IJEDR1502231Page Number(s) - 1420-1425Pubished in - Volume 3 | Issue 2 | May 2015DOI (Digital Object Identifier) - Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Shashank Uniyal, Rajeev Kumar, Krishna Chandra, Vishal Ramola, "Low power explicit type pulse-triggered FF (P-FF) design at Minimum Transistor", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 2, pp.1420-1425, May 2015, Available at :http://www.ijedr.org/papers/IJEDR1502231.pdf
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