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INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH
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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Details
Paper Title
Design and Simulation of Quaternary Logic Gates
Authors
  Dhara Anil Pandya

Abstract
—Multiple-valued logic circuits have received an increased attention in recent years, due to possibility of reduction in number of interconnections and the potential for increased information content per unit chip area. With an increasing density of the chips, the number of inter chip connections is greatly increased as more and more functions are put on the same chip. The quaternary logic cells design of inverter, NAND and NOR with quaternary inputs and quaternary outputs are represented in this paper. Physical design of the logic circuits is simulated and correctness of the results is verified with TANNER tool at 250nm CMOS technology.

Keywords- MVL, CMOS, NMIN, NMAX, VLSI, quaternary, SPICE.
Publication Details
Unique Identification Number - IJEDR1402088
Page Number(s) - 1835-1839
Pubished in - Volume 2 | Issue 2 | June 2014
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Dhara Anil Pandya,   "Design and Simulation of Quaternary Logic Gates", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 2, pp.1835-1839, June 2014, Available at :http://www.ijedr.org/papers/IJEDR1402088.pdf
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