Design and Simulation of Quaternary Logic Gates
Dhara Anil Pandya
—Multiple-valued logic circuits have received an increased attention in recent years, due to possibility of
reduction in number of interconnections and the potential for increased information content per unit chip area. With an
increasing density of the chips, the number of inter chip connections is greatly increased as more and more functions are
put on the same chip. The quaternary logic cells design of inverter, NAND and NOR with quaternary inputs and
quaternary outputs are represented in this paper. Physical design of the logic circuits is simulated and correctness of the
results is verified with TANNER tool at 250nm CMOS technology.
Keywords- MVL, CMOS, NMIN, NMAX, VLSI, quaternary, SPICE.
Cite this Article
Dhara Anil Pandya,   "Design and Simulation of Quaternary Logic Gates"
, International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 2, pp.1835-1839, June 2014, Available at :http://www.ijedr.org/papers/IJEDR1402088.pdf