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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Online Testable Reversible Circuits using reversible gate
  Pooja Rawat,  Vishal Ramola

Abstract –Reversible logic is very promising due to its low power consumption. As the advancement of nanometer technology transient fault occur during the operation of circuit. Traditional technique such as Triple modular redundancy (TMR) consumes large area and power. So overall power dissipation of the chip increases. Reversible logic gaining interest due to low power consumption. This paper proposes the Automatic conversion of any reversible circuit to online testable circuit that can detect online any single bit error. In this paper conversion of decoder circuit and multiplexer is proposed. The proposed structure has been designed and simulated on XILINX 12.2 tool in Verilog language. Index Terms –reversible logic and gates , garbage, multiplexer,online testing and digital circuits.

Publication Details
Unique Identification Number - IJEDR1602183
Page Number(s) - 1047-1051
Pubished in - Volume 4 | Issue 2 | May 2016
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Pooja Rawat,  Vishal Ramola,   "Online Testable Reversible Circuits using reversible gate", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.4, Issue 2, pp.1047-1051, May 2016, Available at :http://www.ijedr.org/papers/IJEDR1602183.pdf
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