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INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH
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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Details
Paper Title
Implementation of Area Efficient Encoder for 4-Bit Flash ADC
Authors
  Jyothi Kamatam,  Kumaraswamy Gajula,  Y.Aruna Suhasini

Abstract
Abstract - Analog–to-digital converter is an important device has a huge application in today’s digitized world. Flash converter is high speed converter among all other ADCs. This paper concerns the design of Flash type of Analog to Digital Converter (ADC) which is more likely to be used for high quality audio and video signals. Different architectures of encoder are designed to build 4 bit Flash ADC The performance of proposed architecture is compared with other available architectures like multiplexer based direct conversion method, Wallace tree encoder, intermediate gray code based encoder using basic gates and using 2:1 multiplexers. From the study it is obtained that the proposed architecture consumes lesser area. The proposed architecture uses minimum number of multiplexers for the conversion. Design of these circuit use gpdk 180nm technology in cadence tool and simulated using SPECTRE.

Keywords- Flash ADC, Encoder
Publication Details
Unique Identification Number - IJEDR1602241
Page Number(s) - 1354-1358
Pubished in - Volume 4 | Issue 2 | May 2016
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Jyothi Kamatam,  Kumaraswamy Gajula,  Y.Aruna Suhasini,   "Implementation of Area Efficient Encoder for 4-Bit Flash ADC", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.4, Issue 2, pp.1354-1358, May 2016, Available at :http://www.ijedr.org/papers/IJEDR1602241.pdf
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