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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Design of 8 Bit CAM Using MSML Design
  T.Poovika,  J.Geetha Ramani,  G.Naveen Balaji

Proposed Paper contains Master slave match line (MSML) architecture which is implemented in traditional CAM cell for storing 8 bit of data. Objective of the proposed methodology is to improve searching speed with less power consumption. MSML operation depends on two things one is Master Match Line (MML) and slave match line (SML). Design is performed using SPICE in 22nm technology. Various parameters such as temperature, power and delay are calculated for MSML design. Proposed methodology power consumption is found to be 598mw with delay of 5.98ns for 22nm technology.

Keywords- CAM, MSML Architecture
Publication Details
Unique Identification Number - IJEDR1902041
Page Number(s) - 201-205
Pubished in - Volume 7 | Issue 2 | May 2019
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  T.Poovika,  J.Geetha Ramani,  G.Naveen Balaji,   "Design of 8 Bit CAM Using MSML Design", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.7, Issue 2, pp.201-205, May 2019, Available at :http://www.ijedr.org/papers/IJEDR1902041.pdf
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